FIG. 1 shows a block diagram of a conventional Ethernet switching system. As shown, the Ethernet system comprises backplane switches 101 and 102, communicating with each other via a trunk line 103. The Ethernet system also comprises a plurality of line cards, including line cards 104, 105, and 106. Each of the line cards includes a switch, such as a switch 1041 in the line card 104, a switch 1051 in the line card 105, and a switch 1061 in the line card 106. Each of the switches communicates with a backplane switch (either of backplane switches 101 or 102). As a result, the line cards communicate with each other through the switches 1041, 1051 and 1061 and the backplane switches 101 and 102.
In the line card 104, CPUs 1042 and 1043 communicate with each other via a network interface 1045, the switch 1041, and a network interface 1044. In the line card 105, CPUs 1052 and 1053 communicate with each other via a network interface 1055, the switch 1051, and a network interface 1054. In the line card 106, CPUs 1062 and 1063 communicate with each other via a network interface 1065, the switch 1061, and a network interface 1064. A CPU and a network interface may be connected over a bus (e.g. a PCI Express bus), while other lines in the system are Ethernet connections.
It should be noted that the network interface functionality within blocks 1044, 1045, 1054, 1055, 1064 and 1065 may be implemented in any number of ways, whether as a chip, a portion of a chip, a card, or a portion of a card.
An Ethernet switch has information about its own ports, so that the switch can receive a packet and switch it over to the right port by examining the content of the packet and component information inside the switch. The switches do not exchange any information in real time, because of the use of standard Ethernet connectivity.
Congestion can occur in various situations. For example, traffic flow may proceed from the CPU 1063 in the line card 106 to the CPU 1053 in the line card 105 via the switch 1061, the backplane switches 101 and 102, and the switch 1051. Other traffic flow may proceed from the CPU 1052 in the line card 105 to the CPU 1053 in the same line card via the switch 1051. If these two traffic flows try to exit the same egress port of the switch 1051, congestion can occur.
In another example, a first traffic flow may proceed from the CPU 1063 in the line card 106 to the CPU 1053 in the line card 105, and a second traffic flow may proceed from the CPU 1062 in the same line card 106 to the CPU 1042 in the line card 104. The two traffic flows from the same line card go to different respective destination ports. The paths of the two traffic flows partially overlap each other, i.e., the part from the switch 1061 to the backplane switch 102 and then to the backplane switch 101. If the egress port of the switch 1051 is congested, but the switch 1061 does not know about the congestion, the switch 1061 may continue to switch packets from the CPUs 1062 and 1063 based on a predetermined policy. For example, it may provide 50% of the uplink traffic to the traffic flow from the CPU 1062, and the remaining 50% of the uplink traffic to the traffic flow from the CPU 1063. Consequently, although there is no congestion on the path from the CPU 1062 to the CPU 1042, only 50% of the traffic flow from the CPU 1062 will pass to its destination.
However, if the switch 1061 knew about the congestion, it could have employed a packet discard mechanism to remove the packets from the CPU 1063 at the outset, thus reducing the load on the entire switching system, and allowing traffic flow from the CPU 1062 to pass through with higher bandwidth.
Conventionally, the switches communicate the congestion information to one another via a proprietary line 110. However, such a proprietary line is not cost effective.
Therefore, it would be desirable to provide a method and apparatus for communicating congestion information among the switches over a more cost effective route.